Control of the polysilicon gate profile during FET fabrication is necessary to maintain the final gate length, a vital parameter that impacts FET performance. While the profile can be affected by subsequent etch processing steps, the profile is determined mainly during the etching of the polysilicon gate material. The gate etch process typically uses inductively coupled plasma (ICP) to obtain a certain plasma density. The process also employs a radio-frequency (RF) bias power that generates a DC bias voltage (VDC) across the plasma sheath which accelerates ions from the plasma onto the wafer.
The gate profile formed during reactive ion etching affects the gate length and depends to a large extent on the process chemistry and the RF power levels used to generate the plasma and accelerate ions that bombard the wafer. For example, addition of a passivating species, such as oxygen, will lead to more tapered profiles due to the faster accumulation of passivated film on the sidewall of the gate. On the other hand, addition of an etching gas like chlorine will reduce the amount of passivation on the sidewall. If the inductive power deposition is increased, this tends to generate a higher plasma density and increase the dissociation of passivating species that may be in the plasma, which leads to a less tapered/more re-entrant profile. If the RF bias power is increased, more etch by-product species are sputtered from the mask and silicon surfaces and end up redeposited on the sidewall of the gate, which leads to a more tapered profile.
The inductively coupled plasma with an HF bias can provide reasonable profile control. However, use of inductively coupled power can make it difficult to maintain a uniform profile across the entire wafer. This is because an inductively coupled plasma tends to concentrate directly beneath the coils of the inductively coupled RF power applicator or antenna. Due to the intense plasma generation directly beneath the coils, plasma ion density distribution is non-uniform and tends to follow the pattern of the coil antenna. This problem can be mitigated by increasing the gap between the coil antenna and the wafer or by decreasing the pressure, but these actions impose additional constraints on the process, limiting, for example, permitted variation in process gas flow that can be used to control the gate critical dimension (CD).